Pixel circuit, display device, and inspection method

ABSTRACT

Compensate for the variations of threshold voltage of a driving transistor. During the period of the reference signal voltage Vref being set to the signal line DTC, voltage between the gate and source of the driving transistor IOC is made equal to or greater than the threshold voltage of the driving transistor IOC, and the difference in voltage of the reference signal voltage Vref and the reference power supply voltage VreCr is charged to the retentive capacitance IOB. At the same time, the voltage of the source of the said driving transistor IOC is set to the reference power supply voltage VreCr to make the voltage applied to the said light emitting elements equal to or lower than its threshold voltage. Subsequently, while maintaining the voltage applied to the said light emitting elements IOE equal to or lower than its threshold voltage.

TECHNICAL FIELD

The present invention relates to a pixel circuit which drives light emitting elements using a driving transistor, a display device and an inspection method.

BACKGROUND ART

With a display device that uses current drive type light emitting elements, such as an organic EL element (OLED), a driving transistor is normally arranged in a pixel circuit. A display is made by driving the driving transistor based on display signals. However, because OLED is a current driving element, variable output current of the driving transistor is directly connected to a deterioration of visual quality. Therefore, a wide variety of proposals have been made to control variable driving current for example as in patent reference 1.

PRIOR ART REFERENCES Patent References

[Patent reference 1] Japanese unexamined patent application No. 2003-271095

[Patent reference 2] Japanese unexamined patent application No. 2004-191603

GENERAL DESCRIPTION OF THE INVENTION Problems to be Solved by the Invention

A switching transistor is used in the patent reference 1 to control the variation in the driving current, and the source electrode of this switching transistor and the cathode electrode of the light emitting elements are in common. Thus, the source electrode of the switching transistor becomes an open status before the light emitting elements are formed and it is difficult to conduct an inspection in such condition.

To conduct an inspection of pixels before the light emitting elements are formed has been proposed, for example, in patent reference 2. However, this patent reference 2 does not include a method of controlling variations in the driving current, and it is impossible to prevent deterioration of display quality as is.

Means for Solving the Problems

A pixel circuit according to the present invention comprises a sampling transistor which is connected to a signal line by one end and is turned on and off by the first scanning line; a driving transistor with a gate being connected to the other end of the sampling transistor and with a drain being connected to the first power supply; light emitting elements which are connected in between a source of the driving transistor and the second power supply and is driven by the current applied to the said driving transistor; a retentive capacitance connected in between the gate and source of the said driving transistor; and a switching transistor which is arranged in between the source of the said driving transistor and a reference potential line and turned on and off by the second scanning line. The said sampling transistor and the said switching transistor are electrically connected during the period when a reference signal voltage is set to the said signal line, the difference in voltage between a reference signal voltage and a reference potential is charged to the said retentive capacitance under the condition of the voltage between the gate and source of the said driving transistor being equal to or greater than the threshold voltage of the said driving transistor, and the source voltage of the said driving transistor is set to the reference potential in order to make the voltage applied to the said light emitting elements equal to or lower than its threshold voltage. Subsequently, while a reference signal voltage is set to the said signal line, the said sampling transistor and the said switching transistor are electrically connected and by turning off the said switching transistor, the voltage equivalent to the threshold voltage of the said driving transistor is retained by the said retentive capacitance while maintaining the voltage applied to the said light emitting elements below its threshold voltage, and the said sampling transistor is electrically connected to sample the said signal voltage during the period when the display signal voltage is set to the said signal line to superimpose the said signal voltage on the threshold voltage retained by the said retentive capacitance.

Also the present invention is a display device having a plurality of pixels arranged in a matrix, comprising a plurality of signal lines; a signal line driving circuit for driving the plurality of signal lines; a plurality of the first scanning lines; the first scanning line driving circuit for driving this first scanning lines; a plurality of the second scanning lines; the second scanning line driving circuit for driving this first scanning lines; and a reference potential line for supplying reference potential, and each pixel with one end being connected to the signal line comprises a sampling transistor, switched between being on and off by a first scanning line; a driving transistor with a gate connected to the other end of the sampling transistor and a drain connected to the first power supply; a light emitting element which is connected in between the source of the driving transistor and a second power supply and driven by the current applied to the said driving transistor; a retentive capacitance connected to between the gate and source of the said driving transistor; and a switching transistor which is arranged between the source of the said driving transistor and the reference potential line and being switched between being on and off by a second scanning line. The said sampling transistor and the said switching transistor are electrically connected during the period when a reference signal voltage is set to the said signal line, the difference in voltage between a reference signal voltage and a reference potential is charged to the said retentive capacitance under the condition of the voltage between the gate and source of the said driving transistor being equal to or greater than the threshold voltage of the said driving transistor, and the source voltage of the said driving transistor is set to the reference potential in order to make the voltage applied to the said light emitting elements equal to or lower than its threshold voltage. Subsequently, while a reference signal voltage is set to the said signal line, the said sampling transistor and the said switching transistor are electrically connected and by turning off the said switching transistor, the voltage equivalent to the threshold voltage of the said driving transistor is retained by the said retentive capacitance while maintaining the voltage applied to the said light emitting elements equal to or lower than its threshold voltage, and the said sampling transistor is electrically connected to sample the said signal voltage during the period when the display signal voltage is set to the said signal line to superimpose the said signal voltage on the threshold voltage retained by the said retentive capacitance.

Also, it is preferred that the said reference potential line is common for two rows of pixels and arranged in the row direction per two rows of pixels.

Also, it is preferred that the said reference potential line is common for two columns of pixels and arranged in the column direction per two rows of pixels.

It is preferred that the said reference potential lines are connected in a group outside of the display area where the said pixels are arranged.

It is preferred that a probe point which is connected to the said reference potential line is a probe point which can be pointed by probe from outside at least before the said light emitting elements are formed.

Also, it is preferred that the said second scanning line is common for two rows of pixels and arranged in the column direction per 2 rows of pixels.

Also, it is preferred that the current-voltage characteristic of the driving transistor is measured before the said light emitting elements are formed, by connecting a probe to the reference potential line to control the said sampling transistor and the on and off of the switching transistor to detect current which flows out from the reference potential line

Advantages of the Invention

According to the present invention, threshold voltage at which current starts to flow to the driving transistor is corrected in a pixel circuit to make variations in the driving current small. Also, the cost reduction can be realized by not sending defective products to the next step, because pixels can be inspected before the said light emitting elements are formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of the present invention.

FIG. 1B is a block diagram of the present invention.

FIG. 2 is a pixel circuit of the present invention.

FIG. 3 is operation waves of the present invention.

FIG. 4A is an explanatory diagram of the present invention.

FIG. 4B is an explanatory diagram of the present invention.

FIG. 4C is an explanatory diagram of the present invention.

FIG. 4D is an explanatory diagram of the present invention.

FIG. 4E is an explanatory diagram of the present invention.

FIG. 4F is an explanatory diagram of the present invention.

FIG. 4G is an explanatory diagram of the present invention.

FIG. 4H is an explanatory diagram of the present invention.

FIG. 4J is an explanatory diagram of the present invention.

FIG. 4K is an explanatory diagram of the present invention.

FIG. 5A is a block diagram of the present invention.

FIG. 5B is an explanatory diagram of the present invention.

MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be explained based on the figures below.

A block diagram of the entire display device according to the embodiment is indicated in FIG. 1A. As illustrated, pixels 10 are arranged in a matrix in a display area and a column direction signal line DTC for each column of pixels 10, the first scanning lines DSR corresponding to each row of pixels, the second scanning lines RSR corresponding to two rows of pixels, and a reference potential line Vref_r are arranged. Two of the first scanning lines DSR are arranged in between two rows of pixels and are connected to both upper and lower sides of pixels respectively, while the second scanning lines PSR and the reference potential line Vref_r are arranged between rows of pixels where there is no first scanning line DSR arranged, and each are connected to upper and lower pixels.

Also, a signal line driving circuit DR for controlling the column direction signal lines, a first scanning line DSR in the row direction and a first scanning line driving circuit SRI for controlling the same, and a second scanning line drive circuit SR2 for controlling a second scanning line RSR in the row direction are arranged at the periphery of the display section in which pixels 10 are arranged. The second scanning line RSR and the reference potential line Vref_r are commonly connected to the pixels of upper and lower two rows.

Also, the reference potential line Vref_r may be in a line direction. In this case, the reference potential line Vref_r is common for every two lines and connected to the pixels in left and right two lines. The constitution of such is indicated in FIG. 1B. Hereinafter, the reference potential line Vref_r in the row direction will be explained.

The actual structure of a pixel circuit contained in the display device shown in FIG. 1 is shown in FIG. 2. Since the second scanning lines DSR and the reference potential lines Vref_r are each shared by two rows, 2 pixels are illustrated in this figure. As shown in FIG. 2, this pixel circuit comprises a light emitting element 10E which emits light as a result of current flow, such as an OLED (organic EL element), a sampling transistor 10A, a driving transistor 10C, a switching transistors 10D, and a retentive capacitance 10B. A gate of the sampling transistor 10A is connected to the first scanning lines DSR while one end is connected to the column direction signal line DTC and the other end is connected to the gate of the driving transistor 10C. The drain electrode of the driving transistor 10C is connected to the power supply VCC and the source electrode is connected to the anode of a current drive type light emitting elements 10E such as organic EL elements. The cathode of the light emitting elements 10E is connected to a cathode power supply VEE. Also, a retentive capacitance 10B is connected in between the gate of the driving transistor 10C and the source electrode. One end of a switching transistor 10D is connected in between the drain of the driving transistor 10C and the anode of the light emitting elements 10E, and the other end as well as the gate electrode are connected to the neighboring pixels of the switching transistor 10D by the other end and the gate electrode.

In FIG. 2, the upper section is pixel 10, the lower section is pixel 11 and each element in the lower pixel is given symbols 11A to 11E.

Also FIG. 2 is illustrated so as the first scanning line DSR is arranged within a column of a pixel one by one and the number of lines arranged in column is indicated as 1, 3, . . . but for arranging pixels, the first scanning line DSR may be arranged by 2 lines in every other column of a pixel as in FIG. 1A, B which is mentioned above.

FIG. 3 indicates a timing chart. FIGS. 4A to 4K illustrate operations of each step.

FIG. 4A is a light emitting period, and the sampling transistors 10A, the switching transistor 1-D are turned off, while the light emitting elements 10E, 11E emit light as a result of the current which is supplied from the driving transistors 10C, 11E.

FIG. 4B is a threshold detection period, and the sampling transistor 10A is made conductive by making the signal line DTCm a reference potential Vref with the first scanning line DSR being H level. By doing so, the voltage of the gate electrode of the driving transistor 10C becomes Vref. Meanwhile, the voltage of the source electrode of the driving transistor 10C is made Vref_r by turning on the switching transistor 10D with the second scanning line RSR being H level. The difference in voltage of Vref and Vref_r is made greater than the threshold voltage of the driving transistor 10C and the voltages of the source electrode of the driving transistor 10C is made equal to or lower than the threshold voltage Vth_10E of the light emitting elements 10E. That is, it is set to satisfy the following equation: Vgs_10C=Vref−Vref_r>Vth_10C, VEE+Vth_10E>Vref_r

Consequently, although the driving transistor 10 is turned on, current is not applied to the light emitting elements 10E. In the retentive capacitance 10B, Vgs-10C is retained.

FIG. 4C is a sampling period for 2×(n−4)th column and 2×(n−3)th column. It is therefore necessary to ensure that there is no impact on pixels of columns other than this. Thus, the sampling transistors 10A and 11A are therefore made non-conductive.

FIG. 4D is a threshold detection preparation period for pixels. The signal line DTCm is made the reference potential Vref, and the gate electrodes of the driving transistors 10C and 11C are made Vref, and so the sampling transistors 10A and 11A are made conductive. The switching transistors 10D, 11D are made conductive to make the voltage of Vgs_10C, Vgs_11C between the gate electrode and source electrode of the driving transistors 10C, 11C greater than the threshold voltage Vth_10C, Vth_11C and also to make the light emitting elements 10E, 11E equal to or lower than the threshold voltage.

This is expressed in the equations below:

Vgs _(—)10C=Vref−Vref_(—) r>Vth _(—)10C  1

Vgs _(—)11C=Vref−Vref_(—) r>Vth _(—)11C  2

VEE+Vth _(—)10E>Vref_(—) r  3

VEE+Vth _(—)11E>Vref_(—) r  4

The second scanning line here is common per two lines, the pixel having address (2n, m) requires a threshold detection period longer by 1H than the pixel having address (n+1, m). Also in FIG. 3, threshold detection period for the pixel having address (2n, m) is set to 1H, the pixel having address (2n+1, m) is set to 2H, but the steps should be repeated until the conditions of equation 1-4 are met. The retentive capacitance 10B and parasitic capacitance are discharged enough as to satisfy the above equations.

FIG. 4D is a threshold detection period for pixels. The signal line DTCm is made the reference potential Vref, and the gate electrodes of the driving transistors 10C and 11C are made Vref, and so the sampling transistors 10A and 11A are made conductive. In order to detect threshold voltage of the driving transistors 10C, 11C, the switching transistors 10D, 11D are therefore made non-conductive. Consequently, the condition of the driving transistors 10C, 11C being on and no current flows in the light emitting elements 10E, 11E is maintained and the voltage Vgs between the gate electrode and the source electrode of the driving transistors 10C, 11C should be set to the threshold voltage of each transistor. The difference in voltage of Vref and Vref_r is accumulated in the retentive capacitances 10B, 11B which modifies towards the threshold voltage of each transistor.

FIG. 4F is a sampling preparation period of five step F, 2×(n−3)+1th column, 2×(n−2)th column, 2×(n−2)+1th column, 2×(n−1)th column and 2×(n−1)+1th column. It is therefore necessary to ensure that there is no impact on pixels of columns other than this. The sampling transistors 10A and 11A are therefore made non-conductive. In this period the voltage of the previous threshold detection period is retained for each electrode.

The steps of FIGS. 4E and 4E are repeated until the voltage between the gate electrode and the source electrode of the driving transistor Vgs becomes the threshold voltage Vth. In the figures, it is repeated 5 times. At this time, the voltage Vs of the source electrode of the driving transistors 10C, 11C are as below:

Vs _(—)10C=Vref−Vth _(—)10C  5

Vs _(—)11C=Vref−Vth _(—)11C  6

Therefore, Vth_10C, Vth_11C are retained in the retentive capacitances 10B, 11B respectively.

Also at this time, the voltage applied to the light emitting elements 10E, 11E must be less than the threshold voltage Vth_10E, Vth_11E. That is, it must satisfy the following equations:

VEE+Vth _(—)10E>VS _(—)10C  7

VEE+Vth _(—)11E>Vs _(—)11C  8

In regards to 2nth column, Vref must satisfy equation 9 which is obtained from equations 5 and 7, and Vref_r must satisfy equation 1.

VEE+Vth _(—)10E+Vth _(—)10C>Vref  9

FIG. 4G is a sampling period for sampling signal voltage Vsig0 by making the signal lines a desired signal voltage Vsig0 and making the sampling transistor 10A conductive. The gate electrode potential of the driving transistor 10C changes from Vref to Vsig0.

At this time, the source electrode of the driving transistor 10C becomes:

Vs _(—)10C=Vref−Vth_(—)10C+(Vsig0−Vref)×Cap_(—)10E/ (Cap_(—)10B+Cap_(—)10E)+VEE×Cap_(—)10B/(Cap_(—)10B+Cap_(—)10E) ={Cap_(—)10BX(VEE+Vref+Cap_(—)10ExVsig0}/(Cap10B+Cap_(—)10E) −Vth _(—)10C

The voltage between the gate electrode and source electrode becomes:

Vgs _(—)10C=Cap_(—)10B/(Cap_(—)10B+Cap_(—)10E)(Vsig0−VEE−Vref) +Vth _(—)10C

In FIG. 4H, the sampling transistors 10A, 11A are non-conductive, and therefore the potential of the previous step is retained for each electrode.

FIG. 4J is the final threshold detecting period of 2n+1th column, and the sampling transistor 10A is made non-conductive while 11A is conductive.

FIG. 4K is a sampling period for sampling signal voltage Vsig1 by making the signal lines a desired signal voltage Vsig1 at the sampling transistor 11A. The gate electrode potential of the driving transistor 11C changes from Vref to Vsig1.

At this time, the source electrode of the driving transistor 11C becomes:

Vs _(—)11C=Vref−Vth _(—)11C+(Vsig0−Vref)×Cap_(—)11E/(Cap_(—)11B+Cap_(—)11E) +VEE×Cap_(—)11B/(CAp_(—)11B+Cap_(—)11E)

The voltage between the gate electrode and source electrode becomes:

Vgs _(—)11C=Cap_(—)11B/(Cap_(—)11B+Cap_(—)11E) ×(Vsig0−VEE−Vref)+Vth _(—)11E

A characteristic formula for Ids of driving transistors is expressed by Ids=β/2(Vgs−Vth)². If Vgs_10C and Vgs_11C are respectively input, it becomes:

Ids0=β/2{Cap_(—)10B/(Cap_(—)10B+Cap_(—)10E)×(Vsig0−VEE−Vref)²

Ids1=β/2{Cap_(—)11B/(Cap_(—)11B+Cap_(—)11E)×(Vsig1−VEE−Vref)²

The term Vth is corrected, and variations in drive current can be suppressed.

FIG. 5A is an overall view of checking failures in transistors, driving transistors, and switching transistors for sampling signal voltage before light emitting elements are formed. The reference potential lines Vref_r is outside of display area and a certain number of lines are connected in a group. The number of the reference potential lines Vref_r to be bound together is determined considering the number of current measuring device, measuring time and S/N ratio. In the figure, Vref_r_(—)0 and Vref_r_n are bound together. And to one end of the bound reference potential line Vref_r, a probe point for measuring is created.

FIG. 5B indicates a pixel circuit of before light emitting elements 10E are formed and of when checking failures in sampling transistors 10A, driving transistors 10C, and switching transistors 10D which are for sampling signal voltage before light emitting elements are formed. That is, when the light emitting elements 10E are formed, the source of the driving transistor 10C is connected to the anode of the light emitting elements 10E, but this connection does not exist before the light emitting elements 10E are formed.

The sampling transistor 10A and the switching transistor 10D are made conductive and the signal potential is given to the gate electrode of the driving transistor 10C from the signal line DTCm. At this time, the current which flows between the drain electrode and source electrode of the driving transistor 10C is measured at the probe point connected to Vref r to check failures. That is, the second scanning line RSR is made H level and the first scanning line DSR is sequentially made H level. By doing so, the sampling transistors 10A of corresponding pixel are turned on, the potential of the signal line DTC is brought into a pixel, a current corresponding to the current is applied, and the current flowing from the probe point to an external ground is measured using a measuring device to confirm operation of pixel circuit.

In particular, IV characteristics including threshold voltage of the driving transistor 10C in one pixel circuit can be detected.

Also, by turning on the signal line DTC one by one, inspections of pixel is conducted one by one, but failures in elements can be detected when inspecting a group of pixels.

Although a n-channel transistor is used in the embodiment above, p-channel transistor may be used. When a p-channel transistor is used in the driving transistor 10C, the source electrode is arranged on the power supply VCC side and the light emitting elements 10# and the retentive capacitance 10B are also arranged on the power supply VCC side.

According to the embodiment of the present invention, threshold voltage at which current starts to flow to the driving transistor is corrected in each pixel circuit to make variations in the driving current small. Also, when inspection of pixel before light emitting elements are formed, that is, failures in sampling transistors, driving transistors, and switching transistors can be checked before the light emitting elements are formed. Consequently, by not sending failure products to the next step, cost reduction is realized.

DESCRIPTION OF THE SYMBOLS

10, 11 pixels, 10A, 11A sampling transistors, 10B, 11B retentive capacitances, 10C, 11C driving transistors, 10D, 11D switching transistors, 10E, 11E light emitting elements. 

1. A pixel circuit comprising a sampling transistor which is connected to a signal line by one end and is turned on and off by the first scanning line; a driving transistor with a gate being connected to the other end of the sampling transistor and with a drain being connected to the first power supply; light emitting elements which are connected in between a source of the driving transistor and the second power supply and is driven by the current applied to the said driving transistor; a retentive capacitance connected in between the gate and source of the said driving transistor; and a switching transistor which is arranged in between the source of the said driving transistor and a reference potential line and turned on and off by the second scanning line. The said sampling transistor and the said switching transistor are electrically connected during the period when a reference signal voltage is set to the said signal line, the difference in voltage between a reference signal voltage and a reference potential is charged to the said retentive capacitance under the condition of the voltage between the gate and source of the said driving transistor being equal to or greater than the threshold voltage of the said driving transistor, and the source voltage of the said driving transistor is set to the reference potential in order to make the voltage applied to the said light emitting elements equal to or lower than its threshold voltage. Subsequently, while a reference signal voltage is set to the said signal line, the said sampling transistor and the said switching transistor are electrically connected and by turning off the said switching transistor, the voltage equivalent to the threshold voltage of the said driving transistor is retained by the said retentive capacitance while maintaining the voltage applied to the said light emitting elements equal to or lower than its threshold voltage, and the said sampling transistor is electrically connected to sample the said signal voltage during the period when the display signal voltage is set to the said signal line to superimpose the said signal voltage on the threshold voltage retained by the said retentive capacitance.
 2. A display device having a plurality of pixels arranged in a matrix, comprising: a plurality of signal lines; a signal line driving circuit for driving the plurality of signal lines; a plurality of the first scanning lines; the first scanning line driving circuit for driving this first scanning lines; a plurality of the second scanning lines; the second scanning line driving circuit for driving this first scanning lines; and a reference potential line for supplying reference potential, and each pixel with one end being connected to the signal line comprises a sampling transistor, switched between being on and off by a first scanning line; a driving transistor with a gate connected to the other end of the sampling transistor and a drain connected to the first power supply; a light emitting element which is connected in between the source of the driving transistor and a second power supply and driven by the current applied to the said driving transistor; a retentive capacitance connected to between the gate and source of the said driving transistor; and a switching transistor which is arranged between the source of the said driving transistor and the reference potential line and being switched between being on and off by a second scanning line. The said sampling transistor and the said switching transistor are electrically connected during the period when a reference signal voltage is set to the said signal line, the difference in voltage between a reference signal voltage and a reference potential is charged to the said retentive capacitance under the condition of the voltage between the gate and source of the said driving transistor being equal to or greater than the threshold voltage of the said driving transistor, and the source voltage of the said driving transistor is set to the reference potential in order to make the voltage applied to the said light emitting elements below its threshold voltage. Subsequently, while a reference signal voltage is set to the said signal line, the said sampling transistor and the said switching transistor are electrically connected and by turning off the said switching transistor, the voltage equivalent to the threshold voltage of the said driving transistor is retained by the said retentive capacitance while maintaining the voltage applied to the said light emitting elements below its threshold voltage, and the said sampling transistor is electrically connected to sample the said signal voltage during the period when the display signal voltage is set to the said signal line to superimpose the said signal voltage on the threshold voltage retained by the said retentive capacitance.
 3. The display device according to claim 2, where in the said reference potential lines are common for two rows of pixels and arranged in the row direction per two rows of pixels.
 4. The display device according to claim 2, where in the said reference potential lines are common for two columns of pixels and arranged in the column direction per two rows of pixels.
 5. The display device according to claim 2, wherein the said reference potential lines are connected in a group outside of the display area where the said pixels are arranged.
 6. The display device according to claim 5 comprising a probe point which is connected to the said reference potential line and which can be pointed by probe from outside at least before the said light emitting elements are formed.
 7. The display device according to claim 2, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 8. An inspection method of the display device according to claim 2, wherein the current -voltage characteristic of the driving transistor is measured before the said light emitting elements are formed by connecting a probe to the reference potential line to control the said sampling transistor and the on and off of the switching transistor to detect current which flows out from the reference potential line.
 9. The display device according to claim 3, wherein the said reference potential lines are connected in a group outside of the display area where the said pixels are arranged.
 10. The display device according to claim 4, wherein the said reference potential lines are connected in a group outside of the display area where the said pixels are arranged.
 11. The display device according to claim 9 comprising a probe point which is connected to the said reference potential line and which can be pointed by probe from outside at least before the said light emitting elements are formed.
 12. The display device according to claim 10 comprising a probe point which is connected to the said reference potential line and which can be pointed by probe from outside at least before the said light emitting elements are formed.
 13. The display device according to claim 3, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 14. The display device according to claim 4, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 15. The display device according to claim 5, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 16. The display device according to claim 9, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 17. The display device according to claim 10, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 18. The display device according to claim 6, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 19. The display device according to claim 11, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels.
 20. The display device according to claim 12, where in the said second scanning line is common to two rows of pixels and arranged in the column direction per two rows of pixels. 